Year 2010

Refereed Publications – 2010

  1. D. Ghai, S. P. Mohanty, and E. Kougianos, “A Variability Tolerant System-on-Chip Ready Nano-CMOS Analog-to-Digital Converter (ADC)”, Taylor & Francis International Journal of Electronics (IJE), Vol. 97, No. 4, April 2010, pp. 421–440.
  2. S. P. Mohanty, D. Ghai, and E. Kougianos, “A P4VT (Power-Performance-Process-Parasitic-Voltage-Temperature) Aware Dual-VTh Nano-CMOS VCO”, in Proceedings of the 23rd International Conference on VLSI Design (VLSID), pp. 99-104, 2010 (blind review, 70 papers accepted out of 320 submissions, acceptance rate – 21.8%).
  3. G. Thakral, S. P. Mohanty, D. Ghai, and D. K. Pradhan, “A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM”, in Proceedings of the 23rd International Conference on VLSI Design (VLSID), pp. 45-50, 2010 (blind review, 70 papers accepted out of 320 submissions, acceptance rate – 21.8%).
  4. G. Thakral, S. P. Mohanty, D. Ghai, and D. K. Pradhan, “A DOE-ILP Assisted Conjugate-Gradient Approach for Power and Stability Optimization in High-κ/Metal-Gate SRAM“, in Proceedings of the 20th ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 323-328, 2010 (blind review, 30 full papers accepted out of 165 submissions, acceptance rate – 18.1%).
  5. G. Thakral, S. P. Mohanty, D. Ghai, and D. K. Pradhan, “P3 (Power-Performance-Process) Optimization of Nano-CMOS SRAM using Statistical DOE-ILP”, in Proceedings of the 11th International Symposium on Quality Electronic Design (ISQED), pp. 176-183, 2010 (blind review, 84 regular papers and 40 poster papers accepted out of 270 submissions, acceptance rate – 45.9%).